This application claims benefit of priority under 35USC 119 based on Japanese Patent Application No. P2000-290717, filed on Sep. 25, 2000, the entire contents of which are incorporated by reference herein.
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit in which test facilitation technology for system on a chip (SOC) constructed with functional blocks (IP: intellectual property) is improved and an automatic insertion method of the same test facilitation circuit. Particularly the present invention relates to a semiconductor integrated circuit in which an effective, high-quality test on the functional blocks (IPs) provided inside the SOC having few outer terminals is achieved and an automatic insertion method of the same test facilitation circuit.
2. Description of the Related Art
In recent years, a large scale LSI called system on a chip (SOC) has been developed, the SOC including an entire single system. For the SOC, a design technique of integrating the IPs, which are functional blocks for achieving a specified function, has become important. In a test on the SOC, a design method for facilitating a test (design for testability: DFT) on the IPs has been employed. The basic DFT method for the IP in the SOC is classified to two types as follows.
(1) Parallel access insertion (MUX (multiplexer) insertion)
(2) Serial access insertion
The method (1) is capable of controlling directly and observing I/O terminals of the IP in the SOC from outside the SOC through the MUXes. A test pattern (test patterns) can be produced easily by making values about the I/O terminals of an object IP possible to monitor in a logic simulation for the SOC.
FIG. 1 shows the structure of the SOC employing the MUX insertion method, which is according to the prior art. In FIG. 1, an IP 142, which is a test object, exists in an SOC 141. A MUX array 144 is provided between input terminals of an IP 142 and connecting wires from a functional block 143 (logic 1 in FIG. 1, which may be an IP) for ordinary operation. A wire from an input terminal array T11 of the SOC 141 is connected to another input of the MUX array 144. Upon test on the IP 142, a selection signal (generally, input signal to the SOC 141, not shown) to this MUX array 144 selects test data from the input terminal array T11 of the SOC 141, so that data can be applied directly to the IP 142 from outside the SOC 141.
An output from the IP142 is branched at an appropriate position ahead of the functional block 145 (logic 2 in FIG. 1 ), which is an output object and may be an IP. The branched output is connected to an input of the MUX array 146 controlled according to the same selection signal as the input to the IP 142. The MUX array 146 is provided in a connection wiring between the appropriate functional block 145 in the SOC 141 and an output terminal (output circuit) array T12 of the SOC 141. Upon test on the IP 142, the MUX array 146 can select an output from the IP 142, so that the output from the IP 142 can be observed outside the SOC 141.
As for the bi-directional signal terminal of the IP 142, a bi-directional MUX array (generally, composed of bus) 147 is provided between the functional blocks 143, 144 for the normal operation and the bi-directional signal terminal (circuit) array T13. Upon the test time, the bi-directional signal terminals of the IP 142 and the bi-directional signal terminals of the array T13 are enabled to exchange signals according to a selection signal used in the above-described two types of the MUX arrays 144, 146. In order to prevent a conflict of signals on the MUX array 147, a signal (not shown) for determining a signal direction, that is, input to or output from the IP 142, is employed. Consequently, the bi-directional signal terminals of the SOC 141 can be operated as if it is a bi-directional signal terminals of the IP 142. According to the MUX insertion method, the IP 142 in the SOC 141 is tested under the above described system.
On the other hand, in the above described (2), a scan test method is employed basically inside the IP 142 so as to produce a test pattern (test patterns) by automatic test pattern generation (ATPG). The input/output terminals of the IP 142 are provided with F/Fs (flip-flops) corresponding to each terminal, called wrapper, which are connected in series and by inputting a predetermined test pattern successively from outside the SOC 141, its result is observed outside the SOC 141.
Of these methods according to the prior art, the MUX insertion method described in the above (1), although its fault coverage (fault detection rate) is slightly lower as compared to the above described (2) method, accompanies only a slight increase in area of the structure necessary for carrying out a test, and can keep a test execution frequency high. On the other hand, if the number of external terminals of the SOC 141 is smaller than that of the external terminals of the IP 142, this method cannot be applied, so that there is no way but applying the above described (2) method.
As described above, as for the MUX insertion method, which is one of the conventional methods for testing the SOC having the IPs, the structure necessary for the test is small and its test time is short. However, contrary to this, if the number of the external terminals of the SOC is smaller than that of the external terminals of the IP, this method cannot be carried out. On the other hand, although as for the other conventional serial access method, its fault coverage is higher as compared to the above-described MUX insertion method, the structure necessary for the test is enlarged and its test time is prolonged.
According to one aspect of the present invention, there is provided a semiconductor integrated circuit having plural functional blocks (IPs; Intellectual Properties) connected to each other, the semiconductor integrated circuit comprising a selection circuit, a bi-directional selection circuit, the functional block (IP), and a test result storage circuit. The selection circuit selects any one of plural inputs and outputting. The bi-directional selection circuit exchanges data bi-directionally. The functional block (IP) includes an input terminal connected to an output terminal of another functional block (which may be an IP) and an input terminal of the semiconductor integrated circuit through the selection circuit and a bi-directional terminal connected to the bi-directional terminal of another functional block and a bi-directional terminal of the semiconductor integrated circuit through the bi-directional selection circuit. The test result storage circuit functions as a test facilitation circuit such that it is connected to an output terminal of the functional block (IP) which receives test outputs of plural bits (n) in parallel from the functional block (IP), compresses the test output into a signature, and outputs the signature-compressed data from an output terminal of the semiconductor integrated circuit in the unit of m (m less than n) bits which is smaller than the plural (n) bits.
According to another aspect of the present invention, there is provided an automatic insertion method of a test facilitation circuit for inserting the test facilitation circuit into a semiconductor integrated circuit constructed by connecting plural functional blocks (IPs) to each other, the automatic insertion method comprising: inputting relating data of the semiconductor integrated circuit including net data indicating input/output terminal of the semiconductor integrated circuit, input/output terminal available for test for the functional block (IP), input/output terminal of the functional block (IP) which realizes the function of the semiconductor integrated circuit and internal connection of the input/output terminal of the semiconductor integrated circuit and a test pattern (test patterns) for confirming the operation of the semiconductor integrated circuit and relating data of the functional block (IP) including the input/output terminal of the functional block (IP), information describing an operation for realizing the functional block (IP) function, kind of the test facilitation method for checking whether or not there is a problem and a test pattern (test patterns) prepared according to the method; inserting a test result storage circuit which functions as the test facilitation circuit for the functional block (IP) which is a test object into the semiconductor integrated circuit based on the input; and outputting relating information after the insertion of the test facilitation circuit of the semiconductor integrated circuit, including net data of the semiconductor integrated circuit in which the test facilitation circuit is inserted and a test pattern (test patterns) obtained by converting a test pattern (test patterns) of the functional block (IP) so as to be capable of being used in the semiconductor integrated circuit in which the test facilitation circuit is inserted.